# Changelog

This file records production-facing changes to ZVINS2. The project follows
semantic versioning; performance claims are tied to the source, configuration,
toolchain, and board receipt named by each release.

## 0.9.0 - 2026-08-27

ZVINS2 0.9.0 establishes the `veni-vidi-vici` QCS6490 production-candidate
line, forked from upstream `dev` at `d41c3a2`. It is not a declaration that
loop closure is production-qualified.

### Estimator and numerics

- Moved the image frontend, IMU propagation, MSCKF, and EKF-SLAM transaction
  into one signed Hexagon v68 cDSP process using a single HVX-128 context.
- Added guarded f32/HVX update lanes with pristine f64 operands, exact
  fallbacks, residual checks, covariance symmetry repair, and global SPD
  certification before commit.
- Added profile-5 fixed-shape projection, covariance-certificate, rank-k, and
  symmetric-update assembly kernels alongside shape-specific C/HVX paths.
- Preserved the 159-state, nine-clone production shape while retaining
  eleven-clone arena capacity for pressure testing.
- Applied the frozen `D_w` residual consistently through JPL propagation and
  added profile 55 for the full frozen imu2 calibration (`D_a`, `D_w`, sensor
  rotations, and `T_g`) with exact frozen-model bias Jacobians.

### Initialization, frames, and runtime

- Added a Ceres-free moving initializer beside the stationary path, with one
  continuous named gravity gauge across initialization and recovery.
- Made publication use one generation-scoped proper FLU-to-FRD transform after
  native-frame estimation and loop correction.
- Pinned real-time APPS work to QCS6490 CPUs 4-7, requested `SCHED_FIFO` 80,
  locked memory, and kept the opportunistic loop worker outside the RT class.
- Kept loop closure observable and generation-safe, but explicitly WIP until
  field verification and PGO acceptance criteria are met.

### Performance evidence

- Qualified the same 865-epoch board replay at 7.770 ms mean / 27.385 ms max
  for profile 5 and 7.836 ms mean / 30.530 ms max for profile 55.
- Both runs completed every epoch, retained plausible state, and stayed below
  the 33.3 ms 30 Hz deadline. New performance-sensitive changes still require
  a fresh replay and live receipt.

### Build, deployment, and documentation

- Standardized reproducible builds on `voxl-cross-hexagon:V5.0`, Hexagon SDK
  6.6.0.0/tools 19.0.07, and the `qcs6490/dev` dependency lane.
- Added focused simulator, pcycle, packet, and board workflows without putting
  broad test suites on the default production path.
- Bound each signed skel to an SDK validation receipt and a content fingerprint
  of its DSP source. Package and flash preflights reject stale, unsigned,
  wrong-ABI, or package-mismatched skels.
- Made both deployment paths synchronize and hash-check the system and
  app-local FastRPC copies so an old skel cannot win library resolution.
- Added the illustrated architecture/HVX book and GitLab Pages site. CI checks
  TeX structure and publishes the reviewed, checked-in PDF without compiling
  LaTeX during deployment.
- Released ZVINS2-owned source under BSD-3-Clause and tagged all owned C, C++,
  header, inline-C, and Hexagon assembly units with SPDX identifiers.
